The present invention relates to electrical devices, and particularly to vertical devices that extend through or partially through a substrate.
Through-wafer vias are an enabling technology for implementing three dimensional (3D) architectures in multilayer circuits and structures that combine semiconductor circuitry with other devices, such as microelectromechanical systems (MEMS) and electro-optical devices. Such vias permit the routing of signals between separate layers of circuitry, enabling greater processing power and functionality without increasing the lateral footprint of the device. This capability can be very important for applications such as, for example, laser radar, high performance RF subsystems, and high performance electronic imagers using pixel level image processing.
MEMS are very small electromechanical devices that combine many of the most desirable aspects of conventional mechanical and solid state devices. MEMS typically provide compact size and high performance while maintaining the manufacturability of semiconductor devices. These benefits have been demonstrated in a number of different device and application areas, including sensing, optics, communications, and health sciences.
The fabrication of MEMS devices often differs from conventional planar semiconductor devices. By virtue of their mechanical operation, MEMS devices may involve significant physical thickness and high aspect ratios for optimal performance. This has led to the development of a number of fabrication processes and processing tools to realize deep, high aspect ratio features at microdevice dimensions. For the case of Si etching, the use of a high density plasma and time-sequenced etch chemistry can provide high aspect ratio and large etch depths. For example, in devices using capacitive sensing of interdigitated electrodes to detect displacements, the high aspect ratio of the electrodes helps maximize the baseline capacitance and capacitance change for more sensitive detection. Such deep etched structures may have dimensions of about 2 microns wide and from about 20 microns to about 100 microns deep, with a narrow spacing between adjacent features of 2 microns, for example. Such high aspect ratio fabrication processes can be very useful in the implementation of through-wafer interconnects by decreasing the achievable diameter and increasing the achievable lateral density of vias.
Because of the desirability of maintaining a small size in many applications, both semiconductor and MEMS devices may also utilize vias, which provide electrical connections between various portions of the device circuitry by passing through the wafer, substrate, or other layers of the device, thereby enabling the device elements to be stacked in a vertical direction, relative to the plane of the device, rather than being spaced on the device in the horizontal direction relative to one another.
One application that exploits the benefits of 3D integration is that of electronic imaging arrays. The integration of sensor arrays with 3D stacked layers of readout and signal processing circuitry can enable implementation of massively parallel, densely interconnected imaging focal plane architectures, resulting in high resolution, high fill factor pixels, ultra-wide dynamic range, multispectral capability and very fast imaging performance.
Traditional via conductors of this type, however, because of their characteristic coupling to the substrate and other circuit elements and characteristic impedance, may not provide sufficient isolation and/or signal transmission characteristics for high frequency operation. High frequency performance can be limited by transmission loss, reflection loss, radiation, and capacitive coupling from the via itself.
Another area that can be improved with 3D integration is capacitive circuit components. Planar RF filters and switched capacitor bank filters, for example, occupy significant die area and integrated single-chip filters are consequently often limited by die size, since metal-insulator-metal (MIM) capacitors can require substantial die area for large capacitance values. By utilizing vertical capacitor structures, substantial reductions in size can be achieved, with a direct correlation to reduced die cost.
Such vertical capacitor structures could also provide advantages in readout circuits, such as those for electronic imaging applications and active lidar. These circuits use planar capacitors for storage of photogenerated charge. For small pixel devices, the amount of charge storage capacity provided by conventional integrated circuit fabrication technology is limited by the physical constraints of pixel pitch. This limits the maximum achievable full well capacity, and can thus negatively impact important focal plane array characteristics, such as maximum intensity and dynamic range. Having the ability to significantly increase the capacitor size and/or the number of capacitors in a circuit, while preserving small die area, could relax these constraints and allow greater design flexibility and improved device performance.
For these reasons, a need has developed in the art for a vertical device, extending through or partially through a substrate, that can be implemented in electronics applications involving 3D architectures and structures that combine multiple layers of semiconductor circuitry or combine semiconductor circuitry with other devices, as well as employing a fabrication process which enables high density structures and is carried out at sufficiently low temperatures to be compatible with semiconductor circuitry.